Training Quantum Neural Networks Directly on Quantum Hardware

Our paper: arXiv:2606.03517
Authors: Natansh Mathur, Panagiotis Kl. Barkoutsos (IonQ), Masako Yamada (IonQ), Martin Roetteler (IonQ), Iordanis Kerenidis (Quantum Signals)

Quantum neural networks (QNNs) are usually trained in simulation and only run on a quantum computer at the end. This paper shows how to train them on the quantum computer itself, at a cost that stays small as the model grows.

Why we wrote it

Training a QNN on hardware means estimating a gradient for every parameter at every step. With the standard parameter-shift rule, the number of circuits to run grows quadratically with the number of qubits, which makes hardware training impractical beyond toy sizes. We wanted to remove that bottleneck before it becomes the limiting factor for our own quantum models.

How it fits our work

Our quantum research program takes neural networks that already work classically and explores quantum versions of them. Pythia, our foundation model for order-book data, is the model we are exploring quantum and quantum-inspired versions of. Any quantum version has to be trainable on real machines on a realistic budget, and this paper is the first piece of that: a training recipe proven on trapped-ion hardware with IonQ. The test case is clinical data imputation, a demanding public benchmark, but the method is architecture-level and carries over to time-series models like ours.

What it adds to our approach

• A circuit built for training. A logarithmic-depth Butterfly architecture with O(n log n) parameters that keeps the model in a well-behaved subspace.
• Layer-wise training on hardware. Only one small, structured layer is optimised on the quantum computer at a time.
• Parallel gradients. Gates inside a Butterfly layer commute, so all of the layer's gradients come out of a constant number of circuit runs.
• Proof on real hardware. 16-qubit training and 32-qubit inference on IonQ Forte Enterprise, with no loss against simulation.

Key takeaway

Circuit evaluations per optimisation step fall from O(n²) for a generic circuit with the standard parameter-shift rule to O(log n). The saving comes in two steps: the Butterfly architecture cuts the count from order n² to order n log n, and our layer-wise parallel rule cuts it from order n log n to order log n. At 16 qubits that is 16 circuits instead of 512 (32x fewer); at 128 qubits it is 28 instead of 32,768 (about 1,170x fewer). The hardware-trained 16-qubit model reached a downstream AUC of 0.715, level with classical imputation methods of comparable width (MICE 0.714) and within 0.003 of the best classical baseline, with lower variance across runs.

Table 1: Circuit evaluations per gradient step

Read the full paper on arXiv. For questions about our research, contact info[at]quantumsignals.ai.